This application relies for priority upon Korean Patent Application No. 2001-40693, filed on Jul. 7, 2001, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention is related to integrated circuit devices. More particularly, the presents invention relates to a voltage generating circuit for generating a voltage higher than a power supply voltage.
2. Related Art
Recently, there have been many attempts to reduce the power supply voltage of integrated circuit devices. In particular, flash electrically erasable and programmable read only memory (xe2x80x9cflash EEPROMxe2x80x9d) devices have been designed to operate at a very low voltage level (e.g., 2V or lower).
Unfortunately, since erasing or programming the flash EEPROM requires a high voltage (e.g., 10V or higher), a method of generating the high voltage using the low power supply voltage is required. A charge pump circuit is typically used to generate the required high voltage level. Conventional charge pump circuits are able to generate the required high voltage using a power supply voltage of around 3.3-5V. If the power supply voltage is lower than that, however, the pump performance of the charge pump circuit is generally reduced. In the worst case, this may result in the required high voltage not being produced.
An object of the present invention is to provide a charge pump circuit that is capable of producing high pump efficiency at a very low power supply voltage.
Another object of the present invention is to enable a charge pump circuit to generate a high target voltage over a long period of time without sharp reductions in capacity.
In order to attain the above objects, a charge pump circuit includes an input terminal that receives an input voltage and an output terminal that outputs an output voltage. A precharge transistor is connected between a power supply voltage terminal and the input terminal and is turned on and off based on a control signal. A plurality of pump stages are connected in series between the input and output terminals.
Complementary first and second clock signals are also provided. Odd-numbered ones of the pump stages are operated in response to either the first or the second clock signal. Even-numbered ones of the pump stages are operated in response to the other one of the clock signals.
In each pump stage of one embodiment, a charge transfer transistor has a gate terminal, a first terminal, a second terminal, and a bulk terminal. The bulk terminal is floated. A first capacitor is connected between the gate terminal of the charge transfer transistor and one of the first and second clock signals. A second capacitor is connected between the second terminal of the charge transfer transistor and the same clock signal as the first capacitor.
A first control transistor can be provided to control a current flow from the second terminal of the charge transfer transistor to the gate terminal thereof. The first control transistor has a gate and a first terminal connected in common to the gate terminal of the charge transfer transistor, a second terminal connected to the second terminal of the charge transfer transistor, and a bulk terminal that is floated.
A second control transistor can be provided to control a current flow from the gate terminal of the charge transfer transistor to the second terminal thereof. The second control transistor has a gate and a first terminal connected in common to the second terminal of the charge transfer transistor, a second terminal connected to the gate terminal of the charge transfer transistor, and a bulk terminal that is floated. Many other aspects and embodiments are also provided, however, as described in further detail below.